image/svg+xmlBLSMSK — Get Mask Up to Lowest Set BitInstruction Operand EncodingDescriptionSets all the lower bits of the destination operand to “1” up to and including lowest set bit (=1) in the source operand. If source operand is zero, BLSMSK sets all bits of the destination operand to 1 and also sets CF to 1.This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.Operationtemp := (SRC-1) XOR (SRC) ;SF := temp[OperandSize -1];ZF := 0;IF SRC = 0CF := 1;ELSECF := 0;FIDEST := temp;Flags AffectedSF is updated based on the result. CF is set if the source if zero. ZF and OF flags are cleared. AF and PF flag are undefined.Intel C/C++ Compiler Intrinsic EquivalentBLSMSK:unsigned __int32 _blsmsk_u32(unsigned __int32 src);BLSMSK:unsigned __int64 _blsmsk_u64(unsigned __int64 src);SIMD Floating-Point ExceptionsNoneOther ExceptionsSee Table2-29, “Type 13 Class Exception Conditions”.Opcode/InstructionOp/ En64/32-bit ModeCPUID Feature FlagDescriptionVEX.LZ.0F38.W0 F3 /2BLSMSK r32, r/m32VMV/VBMI1Set all lower bits in r32 to “1” starting from bit 0 to lowest set bit in r/m32.VEX.LZ.0F38.W1 F3 /2BLSMSK r64, r/m64VMV/N.E.BMI1Set all lower bits in r64 to “1” starting from bit 0 to lowest set bit in r/m64.Op/EnOperand 1Operand 2Operand 3Operand 4VMVEX.vvvv (w)ModRM:r/m (r)NANA

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