image/svg+xmlBLSI — Extract Lowest Set Isolated BitInstruction Operand EncodingDescriptionExtracts the lowest set bit from the source operand and set the corresponding bit in the destination register. All other bits in the destination operand are zeroed. If no bits are set in the source operand, BLSI sets all the bits in the destination to 0 and sets ZF and CF.This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.Operationtemp := (-SRC) bitwiseAND (SRC); SF := temp[OperandSize -1];ZF := (temp = 0);IF SRC = 0CF := 0;ELSECF := 1;FIDEST := temp;Flags AffectedZF and SF are updated based on the result. CF is set if the source is not zero. OF flags are cleared. AF and PF flags are undefined.Intel C/C++ Compiler Intrinsic EquivalentBLSI:unsigned __int32 _blsi_u32(unsigned __int32 src);BLSI:unsigned __int64 _blsi_u64(unsigned __int64 src);SIMD Floating-Point ExceptionsNoneOther ExceptionsSee Table2-29, “Type 13 Class Exception Conditions”.Opcode/InstructionOp/ En64/32-bit ModeCPUID Feature FlagDescriptionVEX.LZ.0F38.W0 F3 /3BLSI r32, r/m32VMV/VBMI1Extract lowest set bit from r/m32 and set that bit in r32.VEX.LZ.0F38.W1 F3 /3BLSI r64, r/m64VMV/N.E.BMI1Extract lowest set bit from r/m64, and set that bit in r64.Op/EnOperand 1Operand 2Operand 3Operand 4VMVEX.vvvv (w)ModRM:r/m (r)NANA

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