ANDPS—Bitwise Logical AND of Packed Single Precision Floating-Point ValuesInstruction Operand EncodingDescriptionPerforms a bitwise logical AND of the four, eight or sixteen packed single-precision floating-point values from the first source operand and the second source operand, and stores the result in the destination operand.EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAXVL-1:256) of the corresponding ZMM register destination are zeroed.VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding ZMM register destination are zeroed.128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-nation is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding ZMM register destination are unmodified.Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionNP 0F 54 /rANDPS xmm1, xmm2/m128AV/VSSEReturn the bitwise logical AND of packed single-precision floating-point values in xmm1 and xmm2/mem. VEX.128.0F 54 /rVANDPS xmm1,xmm2, xmm3/m128BV/VAVXReturn the bitwise logical AND of packed single-precision floating-point values in xmm2 and xmm3/mem. VEX.256.0F 54 /rVANDPS ymm1, ymm2, ymm3/m256BV/VAVXReturn the bitwise logical AND of packed single-precision floating-point values in ymm2 and ymm3/mem.EVEX.128.0F.W0 54 /rVANDPS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcstCV/VAVX512VLAVX512DQReturn the bitwise logical AND of packed single-precision floating-point values in xmm2 and xmm3/m128/m32bcst subject to writemask k1.EVEX.256.0F.W0 54 /rVANDPS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcstCV/VAVX512VLAVX512DQReturn the bitwise logical AND of packed single-precision floating-point values in ymm2 and ymm3/m256/m32bcst subject to writemask k1.EVEX.512.0F.W0 54 /rVANDPS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcstCV/VAVX512DQReturn the bitwise logical AND of packed single-precision floating-point values in zmm2 and zmm3/m512/m32bcst subject to writemask k1.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (r, w)ModRM:r/m (r)NANABNAModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)NACFullModRM:reg (w)EVEX.vvvv (r)ModRM:r/m (r)NA
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