image/svg+xml ANDN — Logical AND NOT Instruction Operand Encoding Description Performs a bitwise logical AND of inverted second operand (the first source operand) with the third operand (the second source operand). The result is stored in the first operand (destination operand). This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD. Operation DEST := (NOT SRC1) bitwiseAND SRC2; SF := DEST[OperandSize -1]; ZF := (DEST = 0); Flags Affected SF and ZF are updated based on result. OF and CF flags are cleared. AF and PF flags are undefined. Intel C/C++ Compiler Intrinsic Equivalent Auto-generated from high-level language. SIMD Floating-Point Exceptions None Other Exceptions See Table2-29, “Type 13 Class Exception Conditions”. Opcode/InstructionOp/ En 64/32 -bit Mode CPUID Feature Flag Description VEX.LZ.0F38.W0 F2 /r ANDN r32a, r32b, r/m32 RVMV/VBMI1Bitwise AND of inverted r32b with r/m32, store result in r32a. VEX.LZ. 0F38.W1 F2 /r ANDN r64a, r64b, r/m64 RVMV/NEBMI1Bitwise AND of inverted r64b with r/m64, store result in r64a. Op/EnOperand 1Operand 2Operand 3Operand 4 RVMModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)NA This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE .