image/svg+xmlAND—Logical ANDInstruction Operand EncodingDescriptionPerforms a bitwise AND operation on the destination (first) and source (second) operands and stores the result in the destination operand location. The source operand can be an immediate, a register, or a memory location; the destination operand can be a register or a memory location. (However, two memory operands cannot be used in one instruction.) Each bit of the result is set to 1 if both corresponding bits of the first and second operands are 1; otherwise, it is set to 0.This instruction can be used with a LOCK prefix to allow the it to be executed atomically.In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.OpcodeInstructionOp/ En64-bit ModeCompat/Leg ModeDescription24 ibAND AL, imm8IValidValidAL AND imm8.25 iwAND AX, imm16IValidValidAX AND imm16.25 idAND EAX, imm32IValidValidEAX AND imm32.REX.W + 25 idAND RAX, imm32IValidN.E.RAX AND imm32 sign-extended to 64-bits.80 /4 ibAND r/m8, imm8MIValidValidr/m8 AND imm8.REX + 80 /4 ibAND r/m8*, imm8MIValidN.E.r/m8 AND imm8.81 /4 iwAND r/m16, imm16MIValidValidr/m16 AND imm16.81 /4 idAND r/m32, imm32MIValidValidr/m32 AND imm32.REX.W + 81 /4 idAND r/m64, imm32MIValidN.E.r/m64 AND imm32 sign extended to 64-bits.83 /4 ibAND r/m16, imm8MIValidValidr/m16 AND imm8 (sign-extended).83 /4 ibAND r/m32, imm8MIValidValidr/m32 AND imm8 (sign-extended).REX.W + 83 /4 ibAND r/m64, imm8MIValidN.E.r/m64 AND imm8 (sign-extended).20 /rAND r/m8, r8MRValidValidr/m8 AND r8.REX + 20 /rAND r/m8*, r8*MRValidN.E.r/m64 AND r8 (sign-extended).21 /rAND r/m16, r16MRValidValidr/m16 AND r16.21 /rAND r/m32, r32MRValidValidr/m32 AND r32.REX.W + 21 /rAND r/m64, r64MRValidN.E.r/m64 AND r32.22 /rAND r8, r/m8RMValidValidr8 AND r/m8.REX + 22 /rAND r8*, r/m8*RMValidN.E.r/m64 AND r8 (sign-extended).23 /rAND r16, r/m16RMValidValidr16 AND r/m16.23 /rAND r32, r/m32RMValidValidr32 AND r/m32.REX.W + 23 /rAND r64, r/m64RMValidN.E.r64 AND r/m64.NOTES:*In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.Op/EnOperand 1Operand 2Operand 3Operand 4RMModRM:reg (r, w)ModRM:r/m (r)NANAMRModRM:r/m (r, w)ModRM:reg (r)NANAMIModRM:r/m (r, w)imm8/16/32NANAIAL/AX/EAX/RAXimm8/16/32NANA

image/svg+xmlOperationDEST := DEST AND SRC;Flags AffectedThe OF and CF flags are cleared; the SF, ZF, and PF flags are set according to the result. The state of the AF flag is undefined.Protected Mode Exceptions#GP(0)If the destination operand points to a non-writable segment.If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SS segment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.#UD If the LOCK prefix is used but the destination is not a memory operand.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SS segment limit.#UD If the LOCK prefix is used but the destination is not a memory operand.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SS segment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made.#UD If the LOCK prefix is used but the destination is not a memory operand.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a non-canonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.#UD If the LOCK prefix is used but the destination is not a memory operand.

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