image/svg+xmlAESENC—Perform One Round of an AES Encryption FlowInstruction Operand EncodingDescriptionThis instruction performs a single round of an AES encryption flow using one/two/four (depending on vector length) 128-bit data (state) from the first source operand with one/two/four (depending on vector length) round key(s) from the second source operand, and stores the result in the destination operand. Use the AESENC instruction for all but the last encryption rounds. For the last encryption round, use the AESENC-CLAST instruction.VEX and EVEX encoded versions of the instruction allow 3-operand (non-destructive) operation. The legacy encoded versions of the instruction require that the first source operand and the destination operand are the same and must be an XMM register.The EVEX encoded form of this instruction does not support memory fault suppression.OperationAESENC STATE := SRC1;RoundKey := SRC2;STATE := ShiftRows( STATE );STATE := SubBytes( STATE );STATE := MixColumns( STATE );DEST[127:0] := STATE XOR RoundKey;DEST[MAXVL-1:128] (Unmodified)Opcode/InstructionOp/ En64/32-bit ModeCPUID Feature FlagDescription66 0F 38 DC /r AESENC xmm1, xmm2/m128AV/VAESPerform one round of an AES encryption flow, using one 128-bit data (state) from xmm1 with one 128-bit round key from xmm2/m128.VEX.128.66.0F38.WIG DC /rVAESENC xmm1, xmm2, xmm3/m128BV/VAESAVXPerform one round of an AES encryption flow, using one 128-bit data (state) from xmm2 with one 128-bit round key from the xmm3/m128; store the result in xmm1.VEX.256.66.0F38.WIG DC /r VAESENC ymm1, ymm2, ymm3/m256BV/VVAESPerform one round of an AES encryption flow, using two 128-bit data (state) from ymm2 with two 128-bit round keys from the ymm3/m256; store the result in ymm1.EVEX.128.66.0F38.WIG DC /rVAESENC xmm1, xmm2, xmm3/m128CV/VVAESAVX512VLPerform one round of an AES encryption flow, using one 128-bit data (state) from xmm2 with one 128-bit round key from the xmm3/m128; store the result in xmm1.EVEX.256.66.0F38.WIG DC /rVAESENC ymm1, ymm2, ymm3/m256CV/VVAESAVX512VLPerform one round of an AES encryption flow, using two 128-bit data (state) from ymm2 with two 128-bit round keys from the ymm3/m256; store the result in ymm1.EVEX.512.66.0F38.WIG DC /rVAESENC zmm1, zmm2, zmm3/m512CV/VVAESAVX512FPerform one round of an AES encryption flow, using four 128-bit data (state) from zmm2 with four 128-bit round keys from the zmm3/m512; store the result in zmm1.Op/EnTupleOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (r, w)ModRM:r/m (r)NANABNAModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)NACFull MemModRM:reg (w)EVEX.vvvv (r)ModRM:r/m (r)NA

image/svg+xmlVAESENC (128b and 256b VEX encoded versions)(KL,VL) = (1,128), (2,256)FOR I := 0 to KL-1:STATE := SRC1.xmm[i]RoundKey := SRC2.xmm[i]STATE := ShiftRows( STATE )STATE := SubBytes( STATE )STATE := MixColumns( STATE )DEST.xmm[i] := STATE XOR RoundKeyDEST[MAXVL-1:VL] := 0VAESENC (EVEX encoded version)(KL,VL) = (1,128), (2,256), (4,512)FOR i := 0 to KL-1:STATE := SRC1.xmm[i] // xmm[i] is the i’th xmm word in the SIMD registerRoundKey := SRC2.xmm[i]STATE := ShiftRows( STATE )STATE := SubBytes( STATE )STATE := MixColumns( STATE )DEST.xmm[i] := STATE XOR RoundKeyDEST[MAXVL-1:VL] := 0Intel C/C++ Compiler Intrinsic Equivalent(V)AESENC:__m128i _mm_aesenc (__m128i, __m128i)VAESENC __m256i _mm256_aesenc_epi128(__m256i, __m256i);VAESENC __m512i _mm512_aesenc_epi128(__m512i, __m512i);SIMD Floating-Point ExceptionsNoneOther ExceptionsSee Table2-21, “Type 4 Class Exception Conditions”.EVEX-encoded: See Table2-50, “Type E4NF Class Exception Conditions”.

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