image/svg+xmlADDSUBPS—Packed Single-FP Add/SubtractInstruction Operand EncodingDescriptionAdds odd-numbered single-precision floating-point values of the first source operand (second operand) with the corresponding single-precision floating-point values from the second source operand (third operand); stores the result in the odd-numbered values of the destination operand (first operand). Subtracts the even-numbered single-precision floating-point values from the second source operand from the corresponding single-precision floating values in the first source operand; stores the result into the even-numbered values of the destination operand.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-nation is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding YMM register destination are unmodified. See Figure3-4.VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding YMM register destination are zeroed.VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM register or a 256-bit memory location. The destination operand is a YMM register. Opcode/InstructionOp/ En64/32-bit ModeCPUID Feature FlagDescriptionF2 0F D0 /rADDSUBPS xmm1, xmm2/m128RMV/VSSE3Add/subtract single-precision floating-point values from xmm2/m128 to xmm1.VEX.128.F2.0F.WIG D0 /rVADDSUBPS xmm1, xmm2, xmm3/m128RVMV/VAVXAdd/subtract single-precision floating-point values from xmm3/mem to xmm2 and stores result in xmm1.VEX.256.F2.0F.WIG D0 /rVADDSUBPS ymm1, ymm2, ymm3/m256RVMV/VAVXAdd / subtract single-precision floating-point values from ymm3/mem to ymm2 and stores result in ymm1.Op/EnOperand 1Operand 2Operand 3Operand 4RMModRM:reg (r, w)ModRM:r/m (r)NANARVMModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)NA

image/svg+xmlOperationADDSUBPS (128-bit Legacy SSE version)DEST[31:0] := DEST[31:0] - SRC[31:0]DEST[63:32] := DEST[63:32] + SRC[63:32]DEST[95:64] := DEST[95:64] - SRC[95:64]DEST[127:96] := DEST[127:96] + SRC[127:96]DEST[MAXVL-1:128] (Unmodified)VADDSUBPS (VEX.128 encoded version)DEST[31:0] := SRC1[31:0] - SRC2[31:0]DEST[63:32] := SRC1[63:32] + SRC2[63:32]DEST[95:64] := SRC1[95:64] - SRC2[95:64]DEST[127:96] := SRC1[127:96] + SRC2[127:96]DEST[MAXVL-1:128] := 0VADDSUBPS (VEX.256 encoded version)DEST[31:0] := SRC1[31:0] - SRC2[31:0]DEST[63:32] := SRC1[63:32] + SRC2[63:32]DEST[95:64] := SRC1[95:64] - SRC2[95:64]DEST[127:96] := SRC1[127:96] + SRC2[127:96]DEST[159:128] := SRC1[159:128] - SRC2[159:128]DEST[191:160] := SRC1[191:160] + SRC2[191:160]DEST[223:192] := SRC1[223:192] - SRC2[223:192]DEST[255:224] := SRC1[255:224] + SRC2[255:224].Intel C/C++ Compiler Intrinsic EquivalentADDSUBPS:__m128 _mm_addsub_ps(__m128 a, __m128 b)VADDSUBPS:__m256 _mm256_addsub_ps (__m256 a, __m256 b)ExceptionsWhen the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated.Figure 3-4. ADDSUBPS—Packed Single-FP Add/SubtractOM15992ADDSUBPS xmm1, xmm2/m128RESULT:xmm1xmm2/m128xmm1[31:0] - xmm2/m128[31:0][31:0]xmm1[63:32] + xmm2/m128[63:32][63:32]xmm1[95:64] - xmm2/m128[95:64][95:64]xmm1[127:96] + xmm2/m128[127:96][127:96][127:96][95:64][63:32][31:0]

image/svg+xmlSIMD Floating-Point ExceptionsOverflow, Underflow, Invalid, Precision, Denormal.Other ExceptionsSee Table2-19, “Type 2 Class Exception Conditions”.

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