image/svg+xmlADDSS—Add Scalar Single-Precision Floating-Point ValuesInstruction Operand EncodingDescriptionAdds the low single-precision floating-point values from the second source operand and the first source operand, and stores the double-precision floating-point result in the destination operand.The second source operand can be an XMM register or a 64-bit memory location. The first source and destination operands are XMM registers. 128-bit Legacy SSE version: The first source and destination operands are the same. Bits (MAXVL-1:32) of the corresponding the destination register remain unchanged.EVEX and VEX.128 encoded version: The first source operand is encoded by EVEX.vvvv/VEX.vvvv. Bits (127:32) of the XMM register destination are copied from corresponding bits in the first source operand. Bits (MAXVL-1:128) of the destination register are zeroed.EVEX version: The low doubleword element of the destination is updated according to the writemask.Software should ensure VADDSS is encoded with VEX.L=0. Encoding VADDSS with VEX.L=1 may encounter unpre-dictable behavior across different processor generations.Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionF3 0F 58 /rADDSS xmm1, xmm2/m32AV/VSSEAdd the low single-precision floating-point value from xmm2/mem to xmm1 and store the result in xmm1.VEX.LIG.F3.0F.WIG 58 /rVADDSS xmm1,xmm2, xmm3/m32BV/VAVXAdd the low single-precision floating-point value from xmm3/mem to xmm2 and store the result in xmm1.EVEX.LLIG.F3.0F.W0 58 /rVADDSS xmm1{k1}{z}, xmm2, xmm3/m32{er}CV/VAVX512FAdd the low single-precision floating-point value from xmm3/m32 to xmm2 and store the result in xmm1with writemask k1.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (r, w)ModRM:r/m (r)NANABNAModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)NACTuple1 ScalarModRM:reg (w)EVEX.vvvv (r)ModRM:r/m (r)NA

image/svg+xmlOperationVADDSS (EVEX encoded versions)IF (EVEX.b = 1) AND SRC2 *is a register*THENSET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);ELSE SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);FI;IF k1[0] or *no writemask*THENDEST[31:0] := SRC1[31:0] + SRC2[31:0]ELSE IF *merging-masking*; merging-maskingTHEN *DEST[31:0] remains unchanged*ELSE ; zeroing-maskingTHEN DEST[31:0] := 0FI;FI;DEST[127:32] := SRC1[127:32]DEST[MAXVL-1:128] := 0VADDSS DEST, SRC1, SRC2 (VEX.128 encoded version)DEST[31:0] := SRC1[31:0] + SRC2[31:0]DEST[127:32] := SRC1[127:32]DEST[MAXVL-1:128] := 0ADDSS DEST, SRC (128-bit Legacy SSE version)DEST[31:0] := DEST[31:0] + SRC[31:0]DEST[MAXVL-1:32] (Unmodified)Intel C/C++ Compiler Intrinsic EquivalentVADDSS __m128 _mm_mask_add_ss (__m128 s, __mmask8 k, __m128 a, __m128 b);VADDSS __m128 _mm_maskz_add_ss (__mmask8 k, __m128 a, __m128 b);VADDSS __m128 _mm_add_round_ss (__m128 a, __m128 b, int);VADDSS __m128 _mm_mask_add_round_ss (__m128 s, __mmask8 k, __m128 a, __m128 b, int);VADDSS __m128 _mm_maskz_add_round_ss (__mmask8 k, __m128 a, __m128 b, int);ADDSS __m128 _mm_add_ss (__m128 a, __m128 b);SIMD Floating-Point ExceptionsOverflow, Underflow, Invalid, Precision, DenormalOther ExceptionsVEX-encoded instruction, see Table2-20, “Type 3 Class Exception Conditions”.EVEX-encoded instruction, see Table2-47, “Type E3 Class Exception Conditions”.

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