image/svg+xmlADDSD—Add Scalar Double-Precision Floating-Point ValuesInstruction Operand EncodingDescriptionAdds the low double-precision floating-point values from the second source operand and the first source operand and stores the double-precision floating-point result in the destination operand.The second source operand can be an XMM register or a 64-bit memory location. The first source and destination operands are XMM registers. 128-bit Legacy SSE version: The first source and destination operands are the same. Bits (MAXVL-1:64) of the corresponding destination register remain unchanged.EVEX and VEX.128 encoded version: The first source operand is encoded by EVEX.vvvv/VEX.vvvv. Bits (127:64) of the XMM register destination are copied from corresponding bits in the first source operand. Bits (MAXVL-1:128) of the destination register are zeroed. EVEX version: The low quadword element of the destination is updated according to the writemask.Software should ensure VADDSD is encoded with VEX.L=0. Encoding VADDSD with VEX.L=1 may encounter unpredictable behavior across different processor generations.Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionF2 0F 58 /rADDSD xmm1, xmm2/m64AV/VSSE2Add the low double-precision floating-point value from xmm2/mem to xmm1 and store the result in xmm1.VEX.LIG.F2.0F.WIG 58 /rVADDSD xmm1, xmm2, xmm3/m64BV/VAVXAdd the low double-precision floating-point value from xmm3/mem to xmm2 and store the result in xmm1.EVEX.LLIG.F2.0F.W1 58 /rVADDSD xmm1 {k1}{z}, xmm2, xmm3/m64{er}CV/VAVX512FAdd the low double-precision floating-point value from xmm3/m64 to xmm2 and store the result in xmm1 with writemask k1.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (r, w)ModRM:r/m (r)NANABNAModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)NACTuple1 ScalarModRM:reg (w)EVEX.vvvv (r)ModRM:r/m (r)NA

image/svg+xmlOperationVADDSD (EVEX encoded version)IF (EVEX.b = 1) AND SRC2 *is a register*THENSET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);ELSE SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);FI;IF k1[0] or *no writemask*THENDEST[63:0] := SRC1[63:0] + SRC2[63:0]ELSE IF *merging-masking*; merging-maskingTHEN *DEST[63:0] remains unchanged*ELSE ; zeroing-maskingTHEN DEST[63:0] := 0FI;FI;DEST[127:64] := SRC1[127:64]DEST[MAXVL-1:128] := 0VADDSD (VEX.128 encoded version)DEST[63:0] := SRC1[63:0] + SRC2[63:0]DEST[127:64] := SRC1[127:64]DEST[MAXVL-1:128] := 0ADDSD (128-bit Legacy SSE version)DEST[63:0] := DEST[63:0] + SRC[63:0]DEST[MAXVL-1:64] (Unmodified)Intel C/C++ Compiler Intrinsic EquivalentVADDSD __m128d _mm_mask_add_sd (__m128d s, __mmask8 k, __m128d a, __m128d b);VADDSD __m128d _mm_maskz_add_sd (__mmask8 k, __m128d a, __m128d b);VADDSD __m128d _mm_add_round_sd (__m128d a, __m128d b, int);VADDSD __m128d _mm_mask_add_round_sd (__m128d s, __mmask8 k, __m128d a, __m128d b, int);VADDSD __m128d _mm_maskz_add_round_sd (__mmask8 k, __m128d a, __m128d b, int);ADDSD __m128d _mm_add_sd (__m128d a, __m128d b);SIMD Floating-Point ExceptionsOverflow, Underflow, Invalid, Precision, DenormalOther ExceptionsVEX-encoded instruction, see Table2-20, “Type 3 Class Exception Conditions”.EVEX-encoded instruction, see Table2-47, “Type E3 Class Exception Conditions”.

This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.