image/svg+xmlADD—AddInstruction Operand EncodingDescriptionAdds the destination operand (first operand) and the source operand (second operand) and then stores the result in the destination operand. The destination operand can be a register or a memory location; the source operand can be an immediate, a register, or a memory location. (However, two memory operands cannot be used in one instruction.) When an immediate value is used as an operand, it is sign-extended to the length of the destination operand format.The ADD instruction performs integer addition. It evaluates the result for both signed and unsigned integer oper-ands and sets the OF and CF flags to indicate a carry (overflow) in the signed or unsigned result, respectively. The SF flag indicates the sign of the signed result.OpcodeInstructionOp/ En64-bit ModeCompat/Leg ModeDescription04 ibADD AL, imm8IValidValidAdd imm8 to AL.05 iwADD AX, imm16IValidValidAdd imm16 to AX.05 idADD EAX, imm32IValidValidAdd imm32 to EAX.REX.W + 05 idADD RAX, imm32IValidN.E.Add imm32 sign-extended to 64-bits to RAX.80 /0 ibADD r/m8, imm8MIValidValidAdd imm8 to r/m8.REX + 80 /0 ibADD r/m8*, imm8MIValidN.E.Add sign-extended imm8 to r/m8.81 /0 iwADD r/m16, imm16MIValidValidAdd imm16 to r/m16.81 /0 idADD r/m32, imm32MIValidValidAdd imm32 to r/m32.REX.W + 81 /0 idADD r/m64, imm32MIValidN.E.Add imm32 sign-extended to 64-bits to r/m64.83 /0 ibADD r/m16, imm8MIValidValidAdd sign-extended imm8 to r/m16.83 /0 ibADD r/m32, imm8MIValidValidAdd sign-extended imm8 to r/m32.REX.W + 83 /0 ibADD r/m64, imm8MIValidN.E.Add sign-extended imm8 to r/m64.00 /rADD r/m8, r8MRValidValidAdd r8 to r/m8.REX + 00 /rADD r/m8*, r8*MRValidN.E.Add r8 to r/m8.01 /rADD r/m16, r16MRValidValidAdd r16 to r/m16.01 /rADD r/m32, r32MRValidValidAdd r32 to r/m32.REX.W + 01 /rADD r/m64, r64MRValidN.E.Add r64 to r/m64.02 /rADD r8, r/m8RMValidValidAdd r/m8 to r8.REX + 02 /rADD r8*, r/m8*RMValidN.E.Add r/m8 to r8.03 /rADD r16, r/m16RMValidValidAdd r/m16 to r16.03 /rADD r32, r/m32RMValidValidAdd r/m32 to r32.REX.W + 03 /rADD r64, r/m64RMValidN.E.Add r/m64 to r64.NOTES:*In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH. Op/EnOperand 1Operand 2Operand 3Operand 4RMModRM:reg (r, w)ModRM:r/m (r)NANAMRModRM:r/m (r, w)ModRM:reg (r)NANAMIModRM:r/m (r, w)imm8/16/32NANAIAL/AX/EAX/RAXimm8/16/32NANA

image/svg+xmlThis instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.OperationDEST := DEST + SRC;Flags AffectedThe OF, SF, ZF, AF, CF, and PF flags are set according to the result.Protected Mode Exceptions#GP(0)If the destination is located in a non-writable segment.If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SS segment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.#UD If the LOCK prefix is used but the destination is not a memory operand.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SS segment limit.#UD If the LOCK prefix is used but the destination is not a memory operand.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SS segment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made.#UD If the LOCK prefix is used but the destination is not a memory operand.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a non-canonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.#UD If the LOCK prefix is used but the destination is not a memory operand.

This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.